#ifndef __DDR_SCAN_OFFLINE_SPRD_R2P0_H__
#define __DDR_SCAN_OFFLINE_SPRD_R2P0_H__

typedef enum
{
	BIST_DS_34OHM = 0,
	BIST_DS_40OHM = 1,
	BIST_DS_48OHM = 2,
	BIST_DS_60OHM = 3,
	BIST_DS_80OHM = 4
}BIST_DS_E;

typedef enum __DMC_DRV_STRENGTH {
	DRV_34_OHM = 0x22,		/*34.3ohm*/
	DRV_40_OHM = 0x28,		/*40ohm*/
	DRV_48_OHM = 0x30,		/*48ohm*/
	DRV_60_OHM = 0x3c,		/*60ohm*/
	DRV_80_OHM = 0x50,		/*80ohm*/
	DRV_120_OHM = 0x78,		/*120ohm*/
}DMC_DRV_STRENGTH;


// 5/10/15/20/25/30  => 240/120/80/60/48/40
typedef enum __DDR_DRV_STRENGTH {
	DRV_40__OHM = 30,
	DRV_48__OHM = 25,
	DRV_60__OHM = 20,
	DRV_80__OHM = 15,
	DRV_120__OHM = 10,
	DRV_240__OHM = 5,
}DDR_DRV_STRENGTH;

typedef enum __PROJECT_ID {
	PROJECT_SHARK	= 0x28300000,
	PROJECT_TSHARK	= 0x28400000,
	PROJECT_PIKE	= 0x28500000,
	PROJECT_PIKEL	= 0x28600000,
	PROJECT_WHALE	= 0x28700000,
	PROJECT_SHARKL2	= 0x28800000,
	PROJECT_SHARKLJ1= 0x28900000,
	PROJECT_PIKE2	= 0x28A00000,
	PROJECT_SHARKLE	= 0x28B00000,
	PROJECT_UNKNOWN	= 0xffffffff,
}PROJECT_ID;

typedef struct __PROJECT_INFO {
	PROJECT_ID id;
	char name[32];
}PROJECT_INFO;

typedef enum __SCAN_DDR_TYPE_ID {
	LPDDR2=0x22222222,
	LPDDR3=0x33333333,
	DDR_UNKNOWN=0xffffffff
}SCAN_DDR_TYPE_ID;

typedef enum
{
	BIST_RES_INVALID = -1,
	BIST_RES_OK    = 0,
	BIST_RES_FAIL = 1
}BIST_RESULT_E;

#define SCAN_ROW1_SYMBOL 0xc1000000
#define SCAN_ROW2_SYMBOL 0xc2000000
#define SCAN_ROW3_SYMBOL 0xc3000000
#define SCAN_ROW4_SYMBOL 0xc4000000
#define SCAN_ROW5_SYMBOL 0xc5000000
#define SCAN_COLUMN1_SYMBOL 0xb1000000
#define SCAN_COLUMN2_SYMBOL 0xb2000000
#define SCAN_COLUMN3_SYMBOL 0xb3000000
#define SCAN_COLUMN4_SYMBOL 0xb4000000

#define REG_AON_APB_RF_BASE 0x327D0000
#define VREF_PHY_START  0x7f
#define VREF_PHY_END  0x0
#define VREF_DDR_START  0x72
#define VREF_DDR_END  0x0
#define VREF_DDR_END_LP3  0x20

#define DDR_FREQ_SHIFT (0xC0*freq_fn)
#define DDR_CHANNEL_NUM 2
#define DDR_BYTE_NUM 2

/*mv*/
#define VDDCORE_STEP 50
#define VDDMEM_STEP 50

#define VDDCORE_STEP_CNT 5
#define VDDMEM_STEP_CNT 5

//#define VDD_CORE_MEM_ADJ
#define DMC_DRV_CFG 30
#define REG_AON_APB_DMC_VREF 0x327D0348
#define CUST_VREF_SHIFT 4
#define CUST_LP3_WR_CA_VREF_MIN (0x50 - CUST_VREF_SHIFT)
#define CUST_LP3_WR_CA_VREF_MAX (0x50 + CUST_VREF_SHIFT)
#define MIN_PASS_WINDOW 16
#define SCAN_FIRST_PASS_FLAG (1 << 0)
#define SCAN_LAST_PASS_FLAG (1 << 1)

#define SCAN_BIST_SIZE 0x2000

typedef enum
{
	VDD_CORE_SET = 1,
	VDD_MEM_SET = 2,
}VOL_SET_FLAG;

#define READ_DQS_NEG  1
#define READ_DQS_POS  0
#define MAX_DQ_DELAY  128

typedef enum __SCAN_IMTE_CODE {
	SCAN_ITEM_BYTE= 0 ,
	SCAN_ITEM_VREF_RD,
	SCAN_ITEM_VREF_CA,  	/*lp4:ca*/
	SCAN_ITEM_VREF_WR,	/*lp4:write*/
	SCAN_ITEM_PHY,
	SCAN_ITEM_DRV,
	SCAN_ITEM_AC_DL,
	SCAN_ITEM_WR_DL,
	SCAN_ITEM_RD_DL,
	SCAN_ITEM_CS,
}SCAN_ITEM_CODE;

#define SCAN_MIDDLE_FLAG (1 << 0)
#define SCAN_START_FLAG (1 << 1)
#define SCAN_END_FLAG (1 << 2)
#define SCAN_VREF_FLAG (1 << 3)
#define SCAN_FST_PAS_FLAG (1 << 4)
#define SCAN_LAST_PAS_FLAG (1 << 5)
#define SCAN_EYE_MASK_LP3_SETUP_LP4_HIGH_FLAG (1 << 6)
#define SCAN_EYE_MASK_LP3_SETUP_LP4_LOW_FLAG (1 << 7)

#define SCAN_EYE_MASK_LP3_HOLD_HIGH_FLAG (1 << 8)
#define SCAN_EYE_MASK_LP3_HOLD_LOW_FLAG (1 << 9)

#define SCAN_ITEM_OFFSET	8

//#define SCAN_USB_LOG_ENABLE

//#define SCAN_LP4_RD_EANBLE
#define SCAN_LP4_CA_EANBLE

#define SCAN_FAIL_PASS_WINDOW (1 << 0)
#define SCAN_FAIL_EYE_MASK (1 << 0)
/*140mv*/
#define LP4_WR_EYE_MASK_VOL_STEP 0x10
#define LP4X_WR_EYE_MASK_VOL_STEP 0x13

#define LP4_RD_EYE_MASK_VOL_STEP 0xD
#define LP4X_RD_EYE_MASK_VOL_STEP 0x17

#define LP4_LP3_MIN_EYE_MASK_PASS_RATE 26
#define LP4_LP3_MIN_PASS_RATE 55

#define LP3_EYE_MASK_VOL_SETUP_STEP 0x17
#define LP3_EYE_MASK_VOL_HOLD_STEP 0x11
#define LP3_RD_EYE_MASK_VOL_STEP 0xD

#define SCAN_RD_ITEM_SHIFT	0
#define SCAN_WR_ITEM_SHIFT	4
#define SCAN_CA_ITEM_SHIFT	8

#define SCAN_READ 0
#define SCAN_WRITE 1

//#define PERBIT_SCAN

void  ddr_scan_offline_r2p0(u32 ddr_clk);
#endif
